Direct memory access (DMA) controllers are well known in the art. One such DMA controller is the .mu.PD71071 manufactured by NEC Electronics Inc. Typically, a DMA controller is configured as a separated integrated circuit chip with input and output pins. The function of this discrete type of DMA controller is to provide high-speed data transfers between peripheral devices and memory or between one memory location and another memory location without the need for the central processor unit (CPU) itself to read or write any data. The DMA controller is programmed by the user with instructions identifying certain data to be transferred from one location to another. When the DMA controller is later given a simple data transfer request, the DMA controller carries out the programmed data transfer instructions. In this way, the CPU is free to perform other operations during the time when the DMA controller is transferring data from one location to another.
In a standard discrete DMA controller such as the .mu.PD71071, a register is included within the DMA controller to temporarily store data during a memory-to-memory transfer. The data read from a source memory location must be temporarily stored in the register located inside the DMA controller until the address of the destination memory location has been provided on the address bus by the DMA controller, and the addressed memory location is ready to receive the data.
When a memory-to-input/output (I/O) device transfer is conducted, the data from the source memory may be applied directly to the input of the I/O device without temporarily storing the data, since no address bits are needed to address the selected I/O device. This is called fly-by DMA.
Additionally, data transfer from an I/O device to a memory location may also be conducted without temporarily storing the data, since once the memory location is addressed, the data from the I/O device may simply be directly read into the addressed location without the need for temporary storage by the CPU or DMA controller.
In microprocessors which include a CPU and a DMA controller, die area may be conserved by eliminating the temporary registers internal to the DMA controller which would be used for temporarily storing data during a direct memory-to-memory transfer. These microprocessors not containing temporary registers in the DMA controller, such as the Model V40 (.mu.PD70208) or V50 (.mu.PD70216) microprocessors by NEC Electronics Inc., are capable of providing direct memory-to-I/O device transfers or I/O device-to-memory transfers but not direct memory-to-memory transfers.
The microprocessors without this direct memory-to-memory transfer feature are generally satisfactory to a user who is willing to use some limited CPU time, and use the registers internal to the CPU, to route data between one memory location and another memory location. However, for some users, it is important that the CPU not expend even this limited CPU processing time conducting memory-to-memory transfers.
Thus, what is needed in the art is a circuit which can be used to quickly and easily enable microprocessors, such as the Model V40 and V50, to have direct memory-to-memory transfer capabilities without requiring manipulation of the data by the CPU.